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ltc3625/ltc3625-1 3625f typical a pplica t ion fea t ures descrip t ion 1a high effciency 2-cell supercapacitor charger with automatic cell balancing the ltc ? 3625/ltc3625-1 are programmable supercapaci- tor chargers designed to charge two supercapacitors in series to a fxed output voltage (4.8v/5.3v or 4v/4.5v selectable) from a 2.7v to 5.5v input supply. automatic cell balancing prevents overvoltage damage to either supercapacitor while maximizing charge rate. no balancing resistors are required. high effciency, high charging current, low quiescent cur- rent and low minimum external parts count (one inductor, one bypass capacitor at v in and one programming resistor) make the ltc3625/ltc3625-1 ideally suited for small form factor backup or high peak power systems. charging current/maximum input current level is pro- grammed with an external resistor. when the input supply is removed and/or the en pin is low, the ltc3625/ltc3625-1 automatically enter a low current state, drawing less than 1a from the supercapacitors. the ltc3625/ltc3625-1 are available in a compact 12-lead 3mm 4mm 0.75mm dfn package. 1a scap charger a pplica t ions n high effciency step-up/step-down charging of two series supercapacitors n automatic cell balancing prevents capacitor overvoltage during charging n programmable charging current up to 500ma (single inductor), 1a (dual inductor) n v in = 2.7v to 5.5v n selectable 2.4v/2.65v regulation per cell (ltc3625) n selectable 2v/2.25v regulation per cell (ltc3625-1) n low no-load quiescent current: 23a n i vout , i vin < 1a in shutdown n low profle 12-lead 3mm 4mm dfn package n servers, raid systems, mass storage, high current backup supplies n solid state hard drives n wireless power meters n high peak power boosted supplies l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. charging two 2:1 mismatched supercapacitors time (seconds) 0 voltage (v) 2 4 6 1 3 5 40 80 120 160 3625 ta01b 200 200 60 100 140 180 v out v mid c top = 50f c bot = 100f r prog = 61.9k ctl = 0 v sel = 0 v out sw1 sw2 v mid pgood pfo ltc3625 3.3h c top 0.1f c bot 0.1f v out 4.8v 3625 ta01a 10f v in 2.7v to 5.5v v in prog 61.9k pfi en ctl v sel 3.3h
ltc3625/ltc3625-1 3625f p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , v out (transient) t < 1ms, duty cycle < 1% .......................................... C0.3v to 7v v in , v out , v mid , pgood, ctl, prog, pfi, pfo ................................... C0.3v to 6v en, v sel ........................................... C0.3v to v in + 0.3v v out short-circuit duration ............................. indefnite i pgood , i pfo ............................................................50ma i prog ........................................................................1ma i vin , i sw1 , i sw2 , i vout (note 2) ...................................3a operating junction temperature range (notes 3, 4) ............................................ C40c to 125c storage temperature range .................. C65c to 125c (note 1) 12 11 10 9 8 7 1 2 3 4 5 6 sw2 v out v mid pgood pfo pfi sw1 v in ctl v sel en prog top view 13 gnd de package 12-lead (4mm s 3mm) plastic dfn t jmax = 125c, q ja = 43c/w exposed pad (pin 13) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3625ede#pbf ltc3625ede#trpbf 3625 12-lead (4mm s 3mm) plastic dfn C40c to 125c ltc3625ede-1#pbf ltc3625ede-1#trpbf 36251 12-lead (4mm s 3mm) plastic dfn C40c to 125c ltc3625ide#pbf ltc3625ide#trpbf 3625 12-lead (4mm s 3mm) plastic dfn C40c to 125c ltc3625ide-1#pbf ltc3625ide-1#trpbf 36251 12-lead (4mm s 3mm) plastic dfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v, r prog = 143k, unless otherwise specifed. symbol parameter conditions min typ max units v in input voltage range l v in(uvlo) 5.5 v v in(uvlo) input undervoltage lockout (v in rising) v sel = v in (ltc3625) v sel = 0v (ltc3625) v sel = 0v or v in (ltc3625-1) l l l 2.8 2.53 2.53 2.9 2.63 2.63 3.0 2.73 2.73 v v v input uvlo hysteresis 100 mv v out(sleep) charger termination voltage v sel = v in (ltc3625) v sel = 0v (ltc3625) v sel = v in (ltc3625-1) v sel = 0v (ltc3625-1) l l l l 5.2 4.7 4.4 3.9 5.3 4.8 4.5 4.0 5.4 4.9 4.6 4.1 v v v v recharge hysteresis below v out(sleep) 135 mv v top , v bot maximum voltage across either of the supercapacitors after charging v sel = v in , v out = 5.3v (ltc3625) v sel = 0v, v out = 4.8v (ltc3625) v sel = v in , v out = 4.5v (ltc3625-1) v sel = 0v, v out = 4v (ltc3625-1) l l l l 2.7 2.45 2.3 2.05 2.75 2.5 2.35 2.1 v v v v maximum supercapacitor offset after charging ctl = 0v ctl = v in 100 50 180 120 mv mv
ltc3625/ltc3625-1 3625f e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v, r prog = 143k, unless otherwise specifed. symbol parameter conditions min typ max units i vin input operating current, i sw1 = i sw2 = 0a, no switching ctl = v in , v mid = 1.5v, v out = 2.5v (boost only) ctl = v in , v mid = 1.5v, v out = 3.5v (buck only) ctl = 0, v mid = 1.5v, v out = 2.5v (buck and boost) 135 275 365 200 400 530 a a a input sleep current v in = 5.5v, v out = 5.4v v in = 3.6v, v out = 5.4v 23 8 35 15 a a input sd current v out = 0v 0 1 a i vout v out sd current v out = 5.4v 0 1 a v out sleep current v out = 5.4v, v in = 3.6v, en = v in v out = 5.4v, v in = 5.5v, en = v in 17 1 25 2.5 a a v prog prog servo voltage v out = 3.5v, v mid = 1.5v l 1.17 1.2 1.23 v h prog ratio of measured i prog current to i buck programmed current 118,000 i buck programmed buck charge current r prog = 143k (note 5) r prog = 71.5k (note 5) 0.88 1.76 0.99 1.98 1.10 2.20 a a i max maximum programmed charge current r prog = 0 (fault condition) (note 5) 1.98 2.65 3.31 a v mid(good) v mid voltage where the boost regulator is enabled 1.35 v v mid(good) hysteresis 150 mv v trickle v out voltage above which boost regulator will exit trickle charge mode and enter normal charge mode v out rising v mid v v trickle falling hysteresis 50 mv i peak(buck) buck charge current peak 1.1 ? i buck a i valley(buck) buck charge current valley 0.9 ? i buck a i peak(boost) boost charge current peak v out = 3v, v mid = 2v (note 5) v out = 1v, v mid = 2v (note 5) 1.59 2.12 200 2.65 a ma i valley(boost) boost charge current valley v out = 3v, v mid = 2v v out = 1v, v mid = 2v 1.41 1.88 0 2.35 a ma maximum boost valley time v out = 1v, v mid = 2v 6.5 s r pmos pmos on-resistance 120 m r nmos nmos on-resistance 100 m i leak sw pin leakage current for sw1, sw2 en = 0v 1 a v pfi pfi falling threshold l 1.17 1.2 1.23 v pfi hysteresis 15 mv i pfi pin leakage current for pfi pin 0 30 na logic (en, ctl, v sel , pgood, pfo) v il input low logic voltage en, ctl, v sel pins l 0.4 v v ih input high logic voltage en, ctl, v sel pins l 1.2 v i il , i ih input low, high current for ctl ctl 1 a r pd en pin pull-down resistance 4.5 m v sel pin pull-down resistance en = v in 4.5 m v ol output low logic voltage pgood, pfo pins; sinking 5ma l 70 200 mv i oh logic high leakage current pgood, pfo pins; pin voltage = 5v 1 a pgood rising threshold v out as a percentage of final target 90 92.5 95 % pgood hysteresis ?v out as a percentage of final target 3 %
ltc3625/ltc3625-1 3625f typical p er f or m ance c harac t eris t ics buck output current vs r prog sleep current vs v in prog voltage and pfi falling threshold vs temperature buck current limits vs temperature t a = 25c, l1 = 3.3h, l2 = 3.3h, c in = 10f, c top = c bot , ltc3625 unless otherwise specifed. e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3625/ltc3625-1 internal switches are guaranteed to survive up to 3a of peak current. internal current limits will restrict peak current to lower levels. note 3: the ltc3625/ltc3625-1 are tested under pulsed load conditions such that t j t a . the ltc3625e/ltc3625e-1 are guaranteed to meet specifcations from 0c to 85c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3625i/ltc3625i-1 are guaranteed over the C40c to 125c operating junction temperature range. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: measurements are tested with ctl = 0v. v in (v) 2.7 3.1 0 current (a) 10 25 i vout i vin 3.5 4.3 4.7 3625 g01 5 20 15 3.9 5.1 5.5 v out = 4.8v v sel = 0v temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 v prog (v) 1.205 1.210 1.215 3625 g02 1.195 1.180 1.220 1.200 1.190 1.185 v in = 3.6v r prog = 143k temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 current (ma) 1050 1100 1150 1200 3625 g03 950 800 1000 900 850 i peak i valley v in = 3.6v r prog = 143k r prog (k) 0 i buck (ma) 1000 2000 3000 500 1500 2500 100 200 300 400 3625 g04 500 500 150 250 350 450 v in = 3.6v v mid = 2v ctl = 0v i prog clamped charge termination error vs temperature temperature (c) ?40 offset (%) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 95 3625 g13 5 35 65 125 80 ?10?25 20 50 110 v in = 3.6v sleep threshold wake threshold input and output sleep currents vs temperature temperature (c) ?40 current (a) 25 20 15 10 5 0 95 3625 g14 5 35 65 125 i vin 80 ?10?25 20 50 110 v in = 3.6v v sel = 3.6v ltc3625-1 i vout v out = 4.5v ltc3625 i vout v out = 5.3v
ltc3625/ltc3625-1 3625f buck input power vs r prog buck effciency vs i buck r prog (k) 0 input power (w) 8 7 6 5 4 3 2 1 0 400 3625 g05 100 200 300 500 350 50 150 250 450 v in = 5.5v v mid = 2.65v ctl = 0v v sel = v in i prog clamped i buck (ma) 200 efficiency (%) 80 90 100 2200 3625 g06 70 60 75 85 95 65 55 50 700 1200 1700 v in = 3.6v v mid = 2v ctl = 0v typical p er f or m ance c harac t eris t ics t a = 25c, l1 = 3.3h, l2 = 3.3h, c in = 10f, c top = c bot , ltc3625 unless otherwise specifed. buck input power vs v mid v mid (v) 0.2 0 input power (w) 1 2 3 4 6 0.6 1.0 1.4 1.8 3625 g07 2.2 2.6 5 v in = 5.5v v sel = v in ctl = 0 r prog = 71.5k r prog = 143k r prog = 286k buck effciency vs v mid buck output current vs v mid v mid (v) 0.2 40 efficiency (%) 50 60 70 80 100 0.6 1.0 1.4 1.8 3625 g08 2.2 2.6 90 v in = 5.5v v sel = v in ctl = 0 r prog = 71.5k r prog = 143k r prog = 286k v mid (v) 0.2 0 i buck (ma) 500 1000 1500 0.6 1.0 1.4 1.8 3625 g09 2.2 2000 2500 250 750 1250 1750 2250 2.6 v in = 5.5v v sel = v in ctl = 0 r prog = 71.5k r prog = 143k r prog = 286k boost input current vs v top v top (v) ?1.5 i boost (ma) 1500 2000 2500 0 1.0 2.5 3625 g10 1000 500 0 ?1.0 ?0.5 0.5 1.5 2.0 v in = 3.6v v mid = 2.5v v top = v out ? v mid ctl = 0 normal operation v out trickle charge operation rfet vs temperature boost effciency vs v top v top (v) ?1.5 efficiency (%) 60 70 80 1.5 3625 g11 50 40 ?0.5 0.5 ?1.0 2.0 0 1.0 2.5 30 20 90 v in = 3.6v v mid = 2.5v v top = v out ? v mid ctl = 0 normal operation v out trickle charge operation temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 pmos r ds(on) () nmos r ds(on) () 0.15 3625 g12 0 0.20 0.10 0.05 0.20 0.05 0.25 0.15 0.10 v in = 2.7v v in = 5.5v pmos nmos charge time vs r prog r prog (k) 0 time (seconds) 400 350 300 250 200 150 100 50 0 400 3625 g15 100 200 300 500 350 50 150 250 450 single inductor application dual inductor application v in = 3.6v v sel = 3.6v v out initial = 0v c top = c bot = 10f i prog clamped
ltc3625/ltc3625-1 3625f typical p er f or m ance c harac t eris t ics t a = 25c, l1 = 3.3h, l2 = 3.3h, c in = 10f, c top = c bot , ltc3625 unless otherwise specifed. sw1 (pin 1): switch pin for the buck regulator. external inductor connects between sw1 pin and v mid . v in (pin 2): input voltage pin. bypass to gnd with a 10f or larger ceramic capacitor. ctl (pin 3): logic input. ctl sets the charge mode of the ltc3625/ltc3625-1. a logic high at ctl programs the part to operate with a single inductor; a logic low programs the part to operate with two inductors. in the 2-inductor application the capacitor stack will charge approximately twice as quickly. ctl is a high impedance input and must be tied to either v in or gnd. do not foat. v sel (pin 4): logic input. v sel selects the output volt- age of the ltc3625/ltc3625-1. a logic low at v sel sets the per-cell maximum voltage to 2.45v/2.05v (v out = 4.8v/4.0v); a logic high sets the per-cell maximum volt- age to 2.70v/2.30v (v out = 5.3v/4.5v). when the part is enabled, v sel has a 4.5m internal pull-down resistor; if en is low, then v sel is a high impedance input pin. en (pin 5): logic input. enables the ltc3625/ltc3625-1. active high. has a 4.5m internal pull-down resistor. charge profle into matched supercaps charge profle with c bot > c top charge profle with c top > c bot p in func t ions prog (pin 6): charge current program pin. connecting a resistor from prog to ground programs the buck output current. this pin servos to 1.2v. pfi (pin 7): input to the power fail comparator. this pin connects to an external resistor divider between v in and gnd. if this functionality is not desired, pfi should be tied to v in . pfo (pin 8): open-drain output of the power-fail compara- tor. the part pulls this pin low if v in is less than a value programmed by an external divider. this pin is active low in shutdown mode. if this functionality is not desired pfo should be left unconnected. pgood (pin 9): logic output. this is an open-drain output which indicates that v out has settled to its fnal value. upon start-up, this pin remains low until the output voltage, v out , is within 92.5% (typical) of its fnal value. once v out is valid, pgood becomes high impedance. if v out falls to 89.5% (typical) of its correct regulation level, pgood is pulled low. pgood may be pulled up through an external resistor to an appropriate reference level. this pin is active low in shutdown mode. time (seconds) 0 single inductor voltage (v) dual inductor voltage (v) 0 2 4 120 3625 g16 6 4 20 40 60 80 100 140 2 0 6 v out v mid v mid v in = 3.6v, v sel = 3.6v r prog = 143k c top = c bot = 10f v out single inductor application dual inductor application time (seconds) 0 single inductor voltage (v) dual inductor voltage (v) 0 2 4 200 3625 g17 6 4 50 100 150 250 2 0 6 v out v mid v mid v in = 3.6v, v sel = 3.6v r prog = 143k c top = 10f, c bot = 50f v out single inductor application dual inductor application time (seconds) 0 single inductor voltage (v) dual inductor voltage (v) 0 2 4 300 3625 g18 6 4 50 100 150 200 250 350 2 0 6 v out v mid v mid v out single inductor application dual inductor application v in = 3.6v, v sel = 3.6v r prog = 143k c top = 50f, c bot = 10f
ltc3625/ltc3625-1 3625f p in func t ions v mid (pin 10): midpoint of two series supercapacitors. the pin voltage is monitored and used, along with v out , to enable or shut down the buck and boost converters during charging to achieve voltage balancing of the top and bottom supercapacitors. v out (pin 11): output voltage pin. connect v out to the positive terminal of the top supercapacitor. the pin volt- age is monitored and used, along with v mid , to enable or shut down the buck and boost converters during charg- ing to achieve voltage balancing of the top and bottom supercapacitors. sw2 (pin 12): switch pin for the boost regulator. external inductor connects between the sw2 pin and v mid . if ctl is logic high, then sw2 must be connected to sw1. gnd (exposed pad pin 13): ground. the exposed pad must be connected to a continuous ground plane on the printed circuit board directly under the ltc3625/ l tc3625 - 1 for electrical contact and to achieve rated thermal performance. b lock diagra m 8 ? + pfo 7 pfi 1.20v 4.44v/4.90v (ltc3625) 3.7v/4.16v (ltc3625-1) 9 ? + pgood 4 v sel 10 v mid threshold detector 5 en 3 ctl v mid_good sd_buck 6 13 2 prog master logic overtemperature shutdown 1.2v ? + ? + gnd sw1 v in b 3625 bd a d sd_boost ref/r programmed avg output current synchronous buck current regulator buck regulator boost regulator 1 11 sw2 v out c 2a avg input current synchronous boost current regulator 12 v maxer v in v out
ltc3625/ltc3625-1 3625f o pera t ion the ltc3625/ltc3625-1 are dual cell supercapacitor char- gers. their unique topology charges two series connected capacitors to a fxed output voltage with programmable charging current without overvoltaging either of the cells even if they are severely mismatched. no balancing resistors are required. the ltc3625/ltc3625-1 include an internal buck converter between v in and v mid to regulate the voltage on c bot (across the bottom capacitor) as well as an internal boost converter between v mid and v out to regulate the voltage on c top (across the top capacitor). the output current of the buck converter is user-programmed via the prog pin and the input current of the boost con- verter is set at 2a (typical). table 1 indicates the various functions of the ltc3625/ ltc3625-1 that can be digitally controlled. table 1. digital input functions pin value function ctl* 0 part runs in 2-inductor application 1 part runs in 1-inductor application v sel 0 4.8v/4.0v sleep threshold 1 5.3v/4.5v sleep threshold en 0 part shuts down, v out becomes high impedance 1 part enables and regulates the output *ctl pin must be hard tied to either v in or gnd. v in undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors v in and keeps the ltc3625/ltc3625-1 disabled until v in rises above 2.90v/2.63v (typical) if v sel is high or 2.63v/2.63v (typical) if v sel is low. hysteresis on the uvlo turns off the ltc3625/ltc3625-1 if v in drops by approximately 100mv below the uvlo rising threshold. when in uvlo, only current needed to detect a valid input will be drawn from v in and v out . buck converter the buck converter regulates a user-programmed average output current given by: i h v r buck prog prog = ? .1 2 where h prog = 118,000 (typical). the buck converter regulates the current hysteretically by switching on the buck pmos until a peak current limit is reached and then turning on the buck nmos until a valley current limit is reached. in the single inductor application the boost nmos is used in conjunction with the buck nmos to increase effciency at high currents. the forward current limit is set to 1.1 ? i buck (typical) and the valley current limit is set to 0.9 ? i buck (typical). because of this method of regulation, overcurrent limit and reverse-current limit protection is automatically provided. the ltc3625/ ltc3625-1 will continue to regulate its programmed cur- rent even into a grounded output. in fault conditions where the prog pin is shorted to ground, or r prog is conductive enough to program i buck to operate outside of specifcation, the current out of the prog pin will be clamped to 22.5a (typical) and i buck will be set to 2.65a (typical). if input current limit is not a concern, the prog pin may be grounded to minimize charge times. boost converter the boost converter regulates a fxed average input current of 2a (typical). the current is regulated hysteretically by switching on the boost nmos until the peak current limit of 2.12a (typical) is reached, and turning on the boost pmos until the valley current limit of 1.88a (typical) is reached. in the single inductor application the buck nmos is used in conjunction with the boost nmos to increase effciency. because of this method of regulation, overcurrent limit and reverse-current limit protection is automatically provided. in normal operation v out will increase with v mid so v out should never be below v mid . in the case where there is a reverse voltage on c top due to a faulty precondition or a large load on the output, the boost converter will operate in trickle charge mode. in this mode the boost pmos gate will remain high and instead allow the sw2 node to increase until sw2 v max + 1v to allow a higher reverse voltage across the inductor, and the current is ramped down to 0ma. this will result in a less effcient charge delivery through the pmos. to keep dissipation low, i peak is limited to 200ma (typical). in this mode the discharge phase is terminated if it lasts longer than 6.5s (typical). the boost converter is disabled if v mid falls below the v mid(good) hysteresis threshold of 1.2v (typical).
ltc3625/ltc3625-1 3625f o pera t ion single inductor operation with the ctl pin tied to v in the ltc3625/ltc3625-1 will operate in single inductor mode. in this mode the same inductor serves in the power path for both the buck and the boost converters. thus, the buck converter and boost converter will never run simultaneously. under certain conditions with a single inductor, a small amount of current can fow from the supercapacitors to v in when the boost charger is active. a 25ma load is required on v in to prevent the v in supply from being pumped to a higher voltage while the boost is active. this minimum load is not needed in the two inductor application and it is also not needed when the charger is disabled. a typical charge cycle for a fully discharged capacitor stack will proceed as follows: 1. the buck converter will turn on and regulate its output current ramping hysteretically between 1.1 ? i buck and 0.9 ? i buck until the v mid(good) threshold is met (1.35v typical). 2. once the v mid(good) threshold is reached, the boost converter will turn on and regulate its input current ramping hysteretically between 2.12a and 1.88a until v mid falls below the v mid(good) hysteresis threshold (1.2v typical). 3. phases 1 and 2 will alternate until v out is approximately 2.4v. when v top (equal to v out C v mid ) is approximately 50mv > v mid , the boost regulator will turn off and the buck regulator will turn on. likewise, when v mid is approximately 50mv > v top , the boost regulator will turn on and the buck regulator will turn off. 4. phase 3 will continue until v out has reached its pro- grammed output voltage. once this happens, the part will enter sleep mode and only minimal power will be consumed (see the electrical characteristics table). 5. if the supercapacitors self discharge or an external load cause the output to drop by more than 135mv (typical), then the ltc3625/ltc3625-1 will exit sleep mode and begin charging the appropriate supercapacitor. in all cases whenever either of the converters is shut down, it will switch to its appropriate discharge phase (nmos on for the buck and pmos on for the boost) until the inductor current reaches 0ma. this optimizes charge delivery to the output capacitors. charge time is dependant on the programmed buck output current as well as the value of the supercapacitors being charged. for estimating charge profles in the single induc- tor application, see the typical performance characteristics graph charge time vs r prog . the effective average v out referred charge current can be approximated as: i i a i a charge buck boost buck ? + 0 5 2 2 . ? ? ? where boost is the boost converter effciency, which is typically about 85% (see the typical performance char- acteristics graph boost effciency vs v top ). seen another way, this is the maximum steady-state load the part can support without losing v out regulation. dual inductor operation with the ctl pin tied to gnd, the ltc3625/ltc3625-1 will operate in dual inductor mode. in this mode two inductors will serve as the power path for the buck and the boost converters. this will allow both the buck and the boost converter to run simultaneously. as a result, the total charge time will be greatly reduced at the cost of an additional board component. a typical charge cycle for a fully discharged capacitor stack will proceed as follows: 1. the buck converter will turn on and regulate its output current ramping hysteretically between 1.1 ? i buck and 0.9 ? i buck until the v mid(good) threshold is met (1.35v typical). 2. once the v mid(good) threshold is reached, the boost converter will turn on and regulate its input current ramping hysteretically between 2.12a and 1.88a. the buck converter will continue to run at the same time. in some cases (i buck ~ <1a) the boost converters input current will exceed the current delivered to c bot ; even though the buck converter is running, charge will be removed and v mid may decrease. thus, if v mid falls below the v mid(good) hysteresis threshold, the boost
ltc3625/ltc3625-1 0 3625f o pera t ion converter will turn off. once v mid has again risen above the v mid(good) threshold, the boost converter will be re-enabled. in the case where v out < v mid , the boost converter will operate in trickle charge mode until v out exceeds v mid (see boost converter). 3. during phase 2, if c bot exceeds its individual maximum threshold voltage (2.45v/2.05v typical if v sel is low or 2.7v/2.3v typical if v sel is high) or if v top exceeds v bot by more than 50mv (typical), then the appropri- ate converter will turn off until the capacitor has fallen below its hysteresis threshold (2.40v/2v typical if v sel is low and 2.65v/2.25v typical if v sel is high for the buck converter or v top < v mid C 50mv typical for the boost converter). 4. once v out has reached its programmed output voltage, the part will enter sleep mode, and only minimal power will be consumed (see the electrical characteristics table). 5. if the supercapacitors self discharge or an external load cause the output to drop by more than 135mv (typical), then the ltc3625/ltc3625-1 will exit sleep mode and begin recharging the supercapacitor stack. in all cases, whenever either of the converters is shut down, it will switch to its appropriate discharge phase (nmos on for the buck and pmos on for the boost) until the inductor current reaches 0ma. this optimizes charge delivery to the output capacitors. charge time is dependent on the programmed buck out- put current as well as the value of supercapacitors being charged. for estimating charge profles in the dual inductor application, see the typical performance characteristics graph charge time vs r prog . the effective average v out referred charge current, while both converters are continuously active, can be approxi- mated as: i i a v v charge buck boost mid out ? ? ? ? ? ? ? 0 5 1 1 2 . ? ? ? ? ? ? and, while both supercapacitors are in balance and v mid is above the v mid(good) threshold as: i charge ? 0.5 ? i buck ? boost where boost is the boost converter effciency which is typically around 85% (see the typical performance char- acteristics graph boost effciency vs v top ). seen another way this is the maximum steady-state load the part can support without losing v out regulation. pgood pin the pgood pin is an open-drain output used to indicate that v out has approached its fnal regulation value. pgood remains active low until v out reaches 92.5% of its regula- tion value at which point it will become high impedance. if v out falls below 89.5% of its regulation voltage after pgood has been asserted, pgood will once again pull active low. pgood is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. pgood is pulled active low in shutdown or input uvlo. power-fail input comparator the pfi/ pfo pins provide an input failure notifcation to the user. the pfi pin is a high impedance input pin that should be tied to a resistive divider from v in . pfo is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. when pfi is above 1.2v, pfo is high impedance and will be pulled up through the external resistor. if pfi drops below 1.2v, pfo will be pulled low indicating a power failure. this allows the user to program any desired input power failure indication threshold. there is 15mv of hysteresis on the pfi pin. if this functionality is not desired the pfi pin should be tied to v in . pfo is pulled active low in shutdown or input uvlo shutdown operation when the en pin is pulled low the ltc3625/ltc3625-1 are put into shutdown. in this case, all of the active circuitry is powered down and there will be less than 1a of leakage current from both v in and v out . this allows the input to be present or absent as well as the capacitor stacks to be fully charged or discharged in shutdown without leakage between v in , v out and gnd.
ltc3625/ltc3625-1 3625f a pplica t ions i n f or m a t ion programming charge current/maximum input current the c bot charge current is programmed with a single resistor connecting the prog pin to ground. the program resistor and buck output current are calculated using the following equation: r h v i prog prog buck = ? .1 2 where h prog = 118,000 (typical). excluding quiescent cur- rent, i buck is always greater than the average buck input current. an r prog resistor value of less than 53.6k will cause the ltc3625/ltc3625-1 to enter overcurrent protec- tion mode and proceed to charge at 2.65a (typical). the effective buck input current can be calculated as: i i v v vin buck buck mid in = ? where buck is the buck converter effciency (see the typical performance characteristics graph buck effciency vs v mid ). output voltage programming the ltc3625/ltc3625-1 have a v sel input pin that allows the user to set the output threshold voltage to either 4.8v/4.0v or 5.3v/4.5v by forcing a low or high at the v sel pin respectively. in the single inductor application the chip will balance the supercapacitors to within 50mv (typical) of each other, resulting in a possible 25mv of over/undercharge per cell. in the dual inductor application the chip will balance the supercapacitors to within 100mv (typical) of each other, resulting in a possible 50mv of over/undercharge per cell. thermal management if the junction temperature increases above approximately 150c, the thermal shutdown circuitry automatically de- activates the output. to reduce the maximum junction temperature, a good thermal connection to the pc board is recommended. connecting the exposed pad (pin 13) of the dfn package to a ground plane under the device on two layers of the pc board, will reduce the thermal resistance of the package and pc board considerably. v in capacitor selection the style and value of capacitors used with the ltc3625/ ltc3625-1 determine input voltage ripple. because the ltc3625/ltc3625-1 use a step-down switching power sup- ply from v in to v mid , its input current waveform contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v in . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v in directly controls the amount of input ripple for a given i buck . increasing the size of this capacitor will reduce the input ripple. multilayer ceramic chip capacitors typically have excep- tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with cau- tion because of their extreme non-linear characteristic of capacitance verse voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal as is expected in-circuit. many vendors specify the capacitance versus voltage with a 1v rms ac test signal and as a result, overstate the capacitance that the capacitor will present in the application. using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler.
ltc3625/ltc3625-1 3625f a pplica t ions i n f or m a t ion the buck and boost converters are designed to work with inductors over a wide range of inductances. choosing a higher valued inductor will decrease operating frequen- cies, while a lower valued inductor will increase frequency but also increase peak current overshoot/undershoot. for most applications a 3.3h inductor is recommended. to maximize effciency, choose an inductor with a low dc resistance. choose an inductor with a dc current rating at least as large as the maximum i peak the application will see according to the specifcations table to ensure that the inductor does not saturate during normal operation. if the single inductor application is used, make sure to size the inductor for the higher of buck or boost peak currents. different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best effciency. the choice of which style inductor to use often depends more on the price versus size, performance and any radiated emi requirements than on what the ltc3625/ltc3625-1 family requires to operate. table 2 shows several inductors that work well with the ltc3625/ltc3625-1 regulators. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. supercapacitor selection the ltc3625/ltc3625-1 are designed to charge super- capacitors of values greater than 0.1f per cell. in general, lower capacitance cells have higher esrs, therefore lower charge currents should be used to help reduce sleep modulation towards the end of a charge cycle. in general, the esr of a supercapacitor cell should not exceed: esr mv i buck 100 where 100mv is the sleep threshold hysteresis. higher capacitance cells typically have lower esrs and can therefore be charged with higher currents. typically, the ltc3625/ltc3625-1 are designed to charge supercapaci- tors with values up to 100f, but higher capacitance cells could be used at the expense of greater charge time. t able 3 shows several supercapacitors that work well with the ltc3625/ltc3625-1. printed circuit board layout considerations in order to be able to deliver maximum current under all conditions, it is critical that the exposed pad on the backside of the ltc3625/ltc3625-1 package be soldered to the pc table 2. inductor manufacturers manufacturer part number inductance (h) current (a) dcr (m) size (mm) coiltronics dr73-3r3-r 3.3 3.0 20 7 7 coilcraft mss7341-332nl 3.3 3.2 20 7 7 vishay ihlm2525czer3r3m11 3.3 6.5 26 6.5 6.9 sumida cdrh6d28p-3ron 3.0 3.0 24 7 7 toko b1077as-3ron 3.0 3.3 30 7.6 7.6 table 3. supercapacitor manufacturers manufacturer part number value (f) operating voltage (v) maximum esr (m) size (mm) cooper bussmann b1860-2r5107-r 100 2.5 20 18 60 illinois capacitor 107dcn2r7m 100 2.7 10 22 45 ness capacitor eshsr-0100c0002r7 100 2.7 9 22 45 tecate tpls-100//22 x 45f 100 2.7 9 22 45 maxwell bcap120p250 120 2.5 2.5 26 51
ltc3625/ltc3625-1 3625f a pplica t ions i n f or m a t ion board ground. failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in higher thermal resistances. furthermore, due to its potentially high frequency switch- ing circuitry, it is imperative that the input capacitor, inductors, and output bypass capacitors be as close to the ltc3625/ltc3625-1 as possible, and that there be an unbroken ground plane under the ic and all of its external high frequency components. high frequency currents, such as the v in and v out currents on the ltc3625/ltc3625-1, tend to fnd their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to fow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. there should be a group of vias under the grounded backside of the pack- age leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be on the highest possible layer of the pc board. any board resistance between inductor(s) and the posi- tive terminal of c bot will add to the capacitors internal esr. likewise, any resistance between the v out pin and the positive terminal of c top will add to its internal esr. any added resistance to the capacitors will reduce the effective charging effciency. in the case of c bot this resistance can be kelvined out by a dedicated voltage sense trace from the v mid pin to a point halfway between the bottom plate of c top and the top plate of c bot . in the case of c top , however, it is even more critical to keep any resistance in the connection to a minimum. excessive series resistance may cause the part to duty cycle in and out of sleep or prematurely shut down the boost, due to the voltage seen at the part being equal to v out + i out ? esr. likewise the c bot supercapacitor should be provided with a low impedance contact to the ground plane with an unbroken, low impedance, path back to the backside of the ltc3625/ltc3625-1 package. when laying out the printed circuit, the following check- list should be used to ensure proper operation of the ltc3625/ltc3625-1. 1. are the bypass capacitors at v in and v out as close as possible to the ltc3625/ltc3625-1? these capacitors provide the ac current to the internal power mosfets and their drivers. minimizing inductance from these capacitors to the ltc3625/ltc3625-1 is a top priority. 2. a re the c bot bypass capacitor and the power inductor(s) closely connected? the (C) terminal of the c bot bypass capacitor returns current to the gnd plane, and then back to c in . 3. keep sensitive components away from the sw pins. 4. keep the current carrying traces from v out to c top and the inductors to c bot to a minimum. typical a pplica t ions 450ma charge current 1-inductor application v out v mid sw2 sw1 r3 71.5k ltc3625-1 prog gnd *25ma minimum load required on v in c2 0.1f c3 0.1f v out 4.0v/4.5v 3625 ta03 c1 10f r1 287k r2 100k v in * 2.7v to 5.5v v in v in v in en ctl v sel pgood pfo pfi l1 3.3h
ltc3625/ltc3625-1 3625f typical a pplica t ions solar powered scap charger with mppt v out sw1 sw2 v mid gnd ctl en pfi v sel gnd r3 143k ltc3625 prog l2 3.3h c2 1f c3 1f 3625 ta04 c1 10f v in l1 3.3h ? + lt1784cs5 v + v ? 1 r5 174k r2 10.0k c4 390f 16v d3 solar panel 6.0v open circuit 4.4v mpp d2 1.2v c5 10nf r1 26.7k r4 10k d1 cmsh3-40 c6 100pf 2 5 3 4 + v out sw1 sw2 v mid gnd pfo ctl 5v en pfi v sel gnd r3 143k ltc3625 prog l1 3.3h c2 100f q1 si4421dy q2 si4421dy c3 100f c1 10f v in r2 100k r1 287k v in gnd ctl sense gate stat ltc4412 v in1 v in2 v out1 fb1 ithm1 fb2 ithm2 gnd gnd v out2 ltm4616 r4 470k r5 4.78k r6 10k 3625 ta05 c7 100f c6 100f 1.8v c8 100f c5 22f 5v power ride-through
ltc3625/ltc3625-1 3625f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion de package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) 4.00 p0.10 (2 sides) 3.00 p0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.70 p 0.10 0.75 p0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 s 45o chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 3.30 p0.10 0.25 p 0.05 0.50 bsc 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 p0.05 0.70 p0.05 3.60 p0.05 package outline 1.70 p 0.05 3.30 p0.05 0.50 bsc 0.25 p 0.05 typical a pplica t ions ? v out sw1 sw2 ctl en gnd v sel v mid ltc3625 prog l2 3.3h c1 100f * m1 irf7424 uv detector *exposed pad to be connected to a thermal pad isolated from the system ground fds3672 v in dc-a 64 lt1737 flyback 2 gnd 12v ? 10 l1 3.3h l4 3.3h l3 3.3h l6 3.3h l5 3.3h c2 100f r1 143k v out ctl en gnd v sel ltc3625 prog c3 100f v in c4 100f r2 143k v out ctl en gnd v sel ltc3625 prog c5 100f v in c6 100f r3 143k fds3672 ltc4355 ideal diode dc/dc ltm4601a v in v out gnd gnd 1.8v gnd dc-b 7 ? 11 dc-c 8 ? 12 lt1737 * sw1 sw2 v mid sw1 sw2 v mid 12v power ride-through
ltc3625/ltc3625-1 3625f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc3203/ltc3203b/ ltc3203b-1/ltc3203-1 500ma low noise high effciency dual mode step-up charge pumps v in : 2.7v to 5.5v, 3mm 3mm 10-lead dfn package ltc3204/ltc3204b-3.3/ ltc3204-5 low noise regulating charge pumps up to 150ma output current (ltc3204-5), up to 50ma output current (ltc3204-3.3) ltc3221/ltc3221-3.3/ ltc3221-5 micropower regulated charge pump up to 60ma output current ltc3225/ltc3225-1 150ma supercapacitor charger programmable supercapacitor charger designed to charge two supercapacitors in series to a fixed output voltage (4.8v/5.3v selectable) from a 2.8v/3v to 5.5v input supply. automatic cell balancing prevents overvoltage damage to either supercapacitor. no balancing resistors are required. ltc3240-3.3/ltc3240-2.5 step-up/step-down regulated charge pumps up to 150ma output current lt ? 3420/lt3420-1 1.4a/1a photofash capacitor charger with automatic top-off charges 220f to 320v in 3.7 seconds from 5v, v in : 2.2v to 16v, i sd < 1a, 10-lead ms package lt3468/lt3468-1/ lt3468-2 1.4a/1a/0.7a, photofash capacitor charger v in : 2.5v to 16v, charge time = 4.6 seconds for the lt3468 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, thinsot tm package ltc3484-0/ltc3484-1/ ltc3484-2 1.4a/0.7a/1a, photofash capacitor charger v in : 1.8v to 16v, charge time = 4.6 seconds for the lt3484-0 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 2mm 3mm 6-lead dfn package lt3485-0/lt3485-1/ lt3485-2/lt3485-3 1.4a/0.7a/1a/2a photofash capacitor charger with output voltage monitor and integrated igbt v in : 1.8v to 10v, charge time = 3.7 seconds for the lt3485-0 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 3mm 3mm 10-lead dfn driver lt3750 capacitor charger controller charges any size capacitor, 10-lead ms package lt3751 capacitor controller with regulation charges any size capacitor, 4mm 5mm qfn-20 package ltc4425 supercapacitor charger with current-limited ideal diode cc/cv linear charger for 2-cell supercapacitor stack from a li-ion/ polymer battery, usb port or a 2.7v to 5.5v current-limited supply, 3mm 3mm dfn-12 and msop-12e packages minimum external component application (500ma charge current) v out sw1 sw2 v mid ltc3625 prog gnd l1 3.3h c2 0.1f v out 4.8v/5.3v c3 0.1f *25ma minimum load required on v in 3625 ta02 c1 10f nc nc v in * 2.7v to 5.5v v in pfi ctl en v sel pgood pfo

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